The amount of silicon “real estate” available for designers of integrated circuits (IC's) acts to limit the number of functional units (transistors, CPU's, memory, etc.) that may be fitted on any given IC. The amount of functionality can be increased by providing shorter transistor gate lengths, however, achievable device densities, as well as signal transmission speeds can be increased only so far, as the state of technology limits gate minimum length to only about 45 nm. The amount of functionality can also be increased by layering chips or dies one on top of another during front-end of the line (FEOL) processing, or by packaging and connecting multiple chips or dies via interposer chips into one discrete unit.
In the layered-device approach, for example as described in U.S. Pat. No. 6,821,826, multiple devices may be built up to a first metal level (FEOL) and then, through a series of wafer bonding processes, the devices may be layered. These aforementioned processes require many complex processing steps. Accurate thermal modeling of the resultant layered structure is very difficult to achieve. For example, it is unknown if heat generated at a lowest layer be adequately removed by a chip package.
Referring to FIG. 1, there is seen an example of one prior art chip-to-chip interconnect solution. In FIG. 1, a first chip 101 is connected to a second chip 103 by an intermediate interposer 102 that includes vias and/or ball solder connections. This method increases IC functionality at a packaging level by packaging multiple devices in close proximity to one another. The advantages of combining multiple types of IC's into one chip are well understood. Exemplary patents include, but are not limited to, U.S. Pat. No. 5,977,640, U.S. Pat. No. 5,362,986, U.S. Pat. No. 5,397,747, U.S. Pat. No. 6,414,374, U.S. Pat No. 6,507,109, U.S. Pat. No. 6,800,505, and U.S. Pat. No. 6,828,173. Many of these patents address the technical solutions needed to stack or place multiple chips. These solutions require the fabrication of custom interposer chips to route signals from one chip to another. If needed, signals may be routed externally through a wirebond or specially made thin film wiring, however, this adds to the complexity and cost of fabricating such prior art “superchip” modules, and because signals have to travel through long interposers, solder, wirebond, and/or other connections, they can become degraded by the associated line resistance and parasitic capacitance.
The present invention addresses these as well as other deficiencies of the prior art.